1. Field of the Invention
The present invention relates to a semiconductor device manufacturing apparatus and a method for manufacturing a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2011-82824, filed Apr. 4, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
With an increase in the level of integration of semiconductor chips in recent years, there have been accompanying advances, with increasing chip sizes and advances in nanoscaling and multi-leveling of interconnects. In order to achieve a higher packaging density, it has become necessary to reduce the package size and thickness.
To accommodate such demands, art regarding MCPs (multichip packages), in which a plurality of semiconductor chips are mounted with high density onto a single interconnect substrate, has been developed. In this art, a CoC (chip-on-chip) type of semiconductor package (semiconductor device), in which a chip stack of semiconductor chips having through electrodes known as TSVs (through silicon vias) is mounted onto the main surface of an interconnect substrate, has gained attention.
When mounting semiconductor chips with high density on an interconnect substrate, a semiconductor device manufacturing apparatus called a bonding apparatus is used.
Japanese Patent Application Publication No. JPA 2005-191053 discloses art of flip-chip mounting a semiconductor chip onto an interconnect substrate, by first applying an NCP (non-conductive paste) to the interconnect substrate and holding the rear surface of a semiconductor chip that has electrodes (bump electrodes) with a vacuum chucking block that has a flat suction chucking surface.
Although it is not a bonding tool, Japanese Patent Application Publication No. JPA 2006-100800 discloses a vacuum chucking nozzle that has a contacting surface that makes contact with a semiconductor chip at the position of the gap between electrodes of the semiconductor chip.